1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a voltage drop circuit for a semiconductor memory device.
2. Description of the Background Art
FIG. 1 is a circuit view illustrating a conventional voltage drop circuit which generates a stable internal voltage Vint. As shown therein, the conventional voltage drop circuit includes a comparator 10, a current supply unit 12 and a load circuit 14.
The comparator 10 includes a current mirror type amplifier and compares voltage levels of predetermined reference voltage Vref and internal voltage Vint using a negative feedback loop. The current supply unit 12 includes a PMOS transistor M1 connected between an external voltage Vext and an output terminal 50 thereof and it is activated in accordance with a comparison signal N1 of the comparator 10. The load circuit 14 is connected between the output terminal 50 and ground voltage Vss, thereby forming the internal voltage Vint in accordance with the current I1 from the current supply unit 12.
The operation of the conventional voltage drop circuit will now be explained.
If the internal voltage Vint is less than the predetermined reference voltage Vref, the comparator 10 outputs the comparison signal N1 at low level and turns on the PMOS transistor M1 of the current supply unit 12. As a result, the predetermined current I1 from the current supply unit 12 flows toward the load circuit 14 so as to form a predetermined level of interval voltage Vint.
When the internal voltage Vint is increased and accordingly the reference voltage Vref is increased, the comparator 10 outputs the comparison signal N1 at high level and turns on the PMOS transistor M1 of the current supply unit 12, whereby the current supply from the current supply unit 12 to the load circuit 14 is interrupted.
Therefore, the conventional voltage drop circuit repeatedly implements the above operation so as to maintain the internal voltage Vint at a constant level.
Presently, as memory capacity becomes highly integrated and miniaturized, an external voltage Vext is decreased to a low voltage (for example, 3.3V.fwdarw.2.5V). Here, when the external voltage Vext is decreased to a low voltage, a voltage Vds between source and drain of the PMOS transistor M1 of the current supply unit 12, thereby deteriorating a current supply capability of the current supply unit 12. As a result, when the load circuit 14 is driven, the internal voltage Vint may be disadvantageously unstable.